(1) FIELD OF THE INVENTION
This invention relates to the fabrication of a semiconductor device, and more specifically to semiconductor devices fabricated from silicon on insulator, (SOI), technology.
(2) DESCRIPTION OF PRIOR ART
A major objective of the semiconductor industry has been to increase the performance of silicon devices while still maintaining, or decreasing the cost of manufacturing silicon devices or chips. These objectives are being partially realized by the ability of the semiconductor industry to achieve micro-miniaturization. The ability to produce silicon devices, with sub-micron features, has resulted in faster performing, and less costly silicon chips. Performance increases have been realized via decreased parasitic capacitances, and decreased resistances, as a result of the smaller device features. In addition smaller features, resulting in smaller silicon chips, allow more chips to be obtained from a specific diameter starting silicon wafer. Therefore for the identical cost of processing a wafer, a greater number of chips can be realized. Micro-miniaturazation has been achieved basically by rapid advances in several critical semiconductor fabrication disciplines. For example in the photolithographic discipline, more sophisticated exposure cameras, as well as more sensitive photoresist materials, have allowed sub-micron images in photoresist to be routinely achieved. In addition similar advances in the dry etching sector have allowed the sub-micron images in photoresist to be successfully transferred to underlying semiconductor materials, used in the fabrication sequence for semiconductor devices. However the approach of continually improving device performance via micro-miniaturazation, can be ultimately limited by the inability of the semiconductor fabrication disciplines to continue their rapid development of tools and materials.
Another approach used to increase device performance, via reductions in parasitic capacitances, is by the silicon on insulator, (SOI), technology. In this technology a thin layer of single crystalline silicon resides on an insulator, which in turn resides on a silicon substrate. The active device regions are created within the SOI layer, therefore unwanted junction capacitances, resulting in part from diffusion to substrate interfaces, are dramatically reduced. The advances in SOI technology have created opportunities for device designers, in regards to for both bipolar junction transistors, (BJT), as well as for metal oxide semiconductor field effect transistors, (MOSFET), devices. In addition semiconductor process sequences can be easily established, via use of the SOI technology, to integrate the BJT and MOSFET processes, to easily create a BiCMOS, (BJT--MOSFET), device. Prior art, such as Houston, et al, in U.S. Pat. No. 5,185,280, and Iwamatsu, et al, in U.S. Pat. No. 5,294,281, have described methods for fabricated integrated circuits using SOI. However these inventions do not show the specific techniques used to produce competitive, or high performing, BJT devices, that this invention will teach. This invention will describe a process sequence for fabricating lateral NPN bipolar junction devices, using SOI technology, with optimized device parameters, such as transistor gain, beta, as well as transistor switching speeds. It will be shown that the process sequences used to achieve this competitive BJT can also be used to simultaneously create MOSFET devices, thus offering a BiCMOS option.